Vertical transport field effect transistor with precise gate length definition

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United States of America Patent

PATENT NO 10014391
SERIAL NO

15195332

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Abstract

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Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.

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Patent Owner(s)

  • IBM CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bergendahl, Marc A Troy, US 98 1147
Cheng, Kangguo Schenectady, US 3065 29546
Lie, Fee Li Albany, US 177 990
Miller, Eric R Schenectady, US 92 893
Sporre, John R Albany, US 86 618
Teehan, Sean Clifton Park, US 72 562

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