Digital phase locked loop for low jitter applications
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United States of America Patent
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Oct 16, 2018
Grant Date -
Dec 28, 2017
app pub date -
Sep 8, 2017
filing date -
Apr 4, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
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