Prefetch bandwidth throttling by dynamically adjusting miss buffer prefetch-dropping thresholds
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United States of America Patent
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May 21, 2019
Grant Date -
Jan 4, 2018
app pub date -
Jun 29, 2016
filing date -
Jun 29, 2016
priority date (Note) -
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Abstract
The disclosed embodiments relate to a method for controlling prefetching in a processor to prevent over-saturation of interfaces in the memory hierarchy of the processor. While the processor is executing, the method determines a bandwidth utilization of an interface from a cache in the processor to a lower level of the memory hierarchy. Next, the method selectively adjusts a prefetch-dropping high-water mark for occupancy of a miss buffer associated with the cache based on the determined bandwidth utilization, wherein the miss buffer stores entries for outstanding demand requests and prefetches that missed in the cache and are waiting for corresponding data to be returned from the lower level of the memory hierarchy, and wherein when the occupancy of the miss buffer exceeds the prefetch-dropping high-water mark, subsequent prefetches that cause a cache miss are dropped.
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