Integrated circuit design verification

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 10073938
APP PUB NO 20180004879A1
SERIAL NO

15196050

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Abstract

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Disclosed aspects relate to verifying an integrated circuit design. A set of design constraints may be received with respect to a verification process for the integrated circuit design. Based on the set of design constraints, a constraint model may be constructed. A new global constraint may be determined using the constraint model. The new global constraint may be used to process the verification process for the integrated circuit design.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINE CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Arunagiri, Anand B Bangalore, IN 3 17
Gajavelly, Raj K Warangal, IN 8 15
Kumar, Sujeet Bangalore, IN 119 3805
Nalla, Pradeep K Bangalore, IN 8 15

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