BUFFERING GRAPHICS TILED RESOURCE TRANSLATIONS IN A DATA PORT CONTROLLER TLB

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United States of America Patent

SERIAL NO

15201497

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Abstract

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Methods and apparatus relating to buffering graphics tiled resource translations in a data port controller TLB (Translation Lookaside Buffer) are described. In an embodiment, controller logic causes storage of information corresponding to a tiled resource in a first entry of a Translation Lookaside Buffer (TLB) in response to a request corresponding to the tiled resource. A second entry of the TLB is capable of storing data corresponding to a coherent memory request. The tiled resource comprise data corresponding to a portion of an image. Other embodiments are also disclosed and claimed.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Appu, Abhishek R El Dorado Hills, US 518 1771
Ray, Joydeep Folsom, US 560 2138
Sodhi, Sandeep S Folsom, US 4 10
Valerio, James A Hillsboro, US 29 237

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