Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
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United States of America Patent
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May 29, 2018
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app pub date -
Jun 20, 2017
filing date -
Jul 1, 2016
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Abstract
A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
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