Clock jitter measurement circuit and semiconductor device including the same
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United States of America Patent
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Jun 5, 2018
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app pub date -
Feb 14, 2017
filing date -
Jul 8, 2016
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Abstract
A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.
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