Memory controller that uses a specific timing reference signal in connection with a data burst following a specified idle period
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 25, 2019
Grant Date -
Jan 11, 2018
app pub date -
Apr 26, 2017
filing date -
Jul 22, 2010
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully