CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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app pub date -
Jul 6, 2017
filing date -
Jul 8, 2016
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Abandoned
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Abstract
A chip package includes a chip, an isolation layer on the bottom surface and the sidewall, a redistribution layer that is on the isolation layer and in electrical contact with a side surface of the conductive pad, and a passivation layer. The chip has a sensor, at least one conductive pad, a top surface, a bottom surface, and a sidewall. The sensor is located on the top surface. The conductive pad is located on an edge of the top surface. The redistribution layer at least partially protrudes from the conductive pad so as to be exposed. The passivation layer is located on the isolation layer and the redistribution layer, such that the redistribution layer not protruding from the conductive pad is between the passivation layer and the isolation layer, and the redistribution layer protruding from the conductive pad is located on the passivation layer.
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