Continuous application and decompression of test patterns and selective compaction of test responses

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United States of America Patent

PATENT NO 10234506
APP PUB NO 20180017622A1
SERIAL NO

15608716

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Abstract

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A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

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Patent Owner(s)

  • MENTOR GRAPHICS CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kassab, Mark Wilsonville, US 46 1680
Mukherjee, Nilanjan Wilsonville, US 100 2978
Rajski, Janusz West Linn, US 141 3796
Tyszer, Jerzy Poznan, PL 86 2715

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