ALLOCATING PHYSICAL PAGES TO SPARSE DATA SETS IN VIRTUAL MEMORY WITHOUT PAGE FAULTING

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United States of America Patent

APP PUB NO 20180024938A1
SERIAL NO

15216071

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Abstract

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A processing system for reduction of a virtual memory page fault rate that includes a first memory to store a dataset, a second memory to store a subset of the dataset, and a processing unit. The processing unit is configured to receive a memory access request including a virtual address and determine whether the virtual address is mapped to a first physical page in the first memory and or a second physical page in the second memory. The processing unit maps a third physical page in a free page pool of the second memory to the virtual address in response to the virtual address not being mapped to the second physical page. The processing unit also grants access to the third physical page that is mapped to the virtual address.

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Patent Owner(s)

Patent OwnerAddress
ADVANCED MICRO DEVICES INC2485 AUGUSTINE DRIVE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brennan, Christopher Boxborough, US 12 140
Paltashev, Timour T Sunnyvale, US 11 103

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