TECHNIQUES TO PROVIDE A MULTI-LEVEL MEMORY ARCHITECTURE VIA INTERCONNECTS

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United States of America Patent

SERIAL NO

15476896

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Abstract

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Various embodiments are generally directed to an apparatus, method and other techniques to enable memory interfaces to communicate read request, write requests, and data via an interconnect. Embodiments, include processing write requests to write data into memory coupled via an interconnect and processing read requests to read data from memory coupled via an interconnect. In embodiments, the data may be compressed data based on a compression mechanism and communicated in a fabric packet including a compression mechanism indicator, the compressed data, and an address, the compression mechanism indicator to indicate which compression mechanism is applied to the data.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
KUMAR, MOHAN J ALOHA, US 227 3050
NACHIMUTHU, MURUGASAMY K BEAVERTON, US 115 1099

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