Methods for an ESD protection circuit including trigger-voltage tunable cascode transistors

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United States of America Patent

PATENT NO 10147715
APP PUB NO 20180026028A1
SERIAL NO

15481202

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Abstract

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Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Chien-hsin Malta, US 51 241
Natarajan, Mahadeva Iyer Clifton Park, US 37 136
Prabhu, Manjunatha Malta, US 31 63

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