Importance

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Abstract

Technology related to out-of-order processor architectures is disclosed. In one example of the disclosed technology, a processor includes decode logic and issue logic. The decode logic is configured to decode a store mask of an instruction block. The instruction block can include load and store instructions. Each load and store instruction includes an identifier specifying a relative program order of the load or store instruction within the instruction block. The store mask identifies positions of the store instructions within the program order of the instruction block. The issue logic is configured to issue at least one of the instructions of the instruction block out of program order. The issue logic can be configured to use the decoded store mask to only issue load instructions after all store instructions preceding the load instructions have issued.

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First Claim