HBM with in-memory cache manager
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United States of America Patent
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Jan 15, 2019
Grant Date -
Feb 1, 2018
app pub date -
Sep 21, 2016
filing date -
Jul 26, 2016
priority date (Note) -
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Abstract
A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.
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