Etch damage and ESL free dual damascene metal interconnect

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 10312136
APP PUB NO 20180033684A1
SERIAL NO

15726590

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Abstract

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Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bao, Tien-I Taoyuan, TW 276 4672
Lee, Chung-Ju Hsinchu, TW 258 4103
Singh, Sunil Kumar Hsinchu, TW 39 180

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