SEMICONDUCTOR ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME

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United States of America Patent

APP PUB NO 20180033699A1
SERIAL NO

15723928

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Abstract

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Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

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Patent Owner(s)

Patent OwnerAddress
INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES100029 BEIJING CITY CHAOYANG DISTRICT BEITUCHENG WEST ROAD NO 3 CHINESE ACADEMY OF SCIENCES INSTITUTE OF MICROELECTRONICS MUNICIPAL DISTRICT BEIJING CITY 100029

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
ZHU, Huilong Poughkeepsie, US 589 8348

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