THREAD BLOCK MANAGING METHOD, WARP MANAGING METHOD AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM CAN PERFORM THE METHODS

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United States of America Patent

SERIAL NO

15485241

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Abstract

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A thread block managing method, applied to an electronic apparatus comprising a memory and a cache, comprising: (a) transforming memory addresses for the memory to cache addresses of the cache; (b) mapping a memory access range for a thread block to the cache addresses to generate a block access range; (c) calculating block locality between the thread blocks according to the block access range; and (d) allocating the thread blocks to a plurality of multi-processors depending on the block locality.

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Patent Owner(s)

Patent OwnerAddress
NATIONAL TAIWAN UNIVERSITYNO 1 SEC 4 ROOSEVELT ROAD TAIPEI 10617
MEDIATEK INCNO 1 DUSING RD 1ST SCIENCE-BASED INDUSTRIAL PARK HSIN-CHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Li-Jhan New Taipei City, TW 1 4
Wang, Po-Han Taipei City, TW 55 133
Yang, Chia-Lin Taipei City, TW 24 220

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