SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER
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United States of America Patent
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app pub date -
Oct 10, 2017
filing date -
Feb 17, 2014
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Abstract
An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.
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