Layer-based memory controller optimizations for three dimensional memory constructs

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United States of America Patent

PATENT NO 10262744
APP PUB NO 20180047453A1
SERIAL NO

15589863

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Abstract

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Disclosed are techniques for selecting one or more reference voltages for performing one or more operations on a memory cell based on a determined layer of a three-dimensional memory construct to which the memory cell belongs. The one or more operations can include read or write operations. The memory cell can be a flash memory cell.

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Patent Owner(s)

  • SK HYNIX INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhatia, Aman San Jose, US 116 432
Cai, Yu San Jose, US 240 1229
Kim, HyungSeok Santa Clara, US 29 88
Pignatelli, David Saratoga, US 21 339
Xiong, Chenrong San Jose, US 68 298
Zhang, Fan Fremont, US 888 6238

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