Method for fabricating transistor with thinned channel

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United States of America Patent

PATENT NO 10367093
APP PUB NO 20180047846A1
SERIAL NO

15730542

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Abstract

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A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brask, Justin K Portland, US 253 8518
Chau, Robert S Beaverton, US 514 18995
Datta, Suman Beaverton, US 256 10425
Doczy, Mark L Beaverton, US 209 5761
Doyle, Brian S Portland, US 369 13967
Kavalieros, Jack T Portland, US 511 7889
Majumdar, Amlan Portland, US 159 3269
Metz, Matthew V Hillsboro, US 331 5773
Radosavljevic, Marko Beaverton, US 465 4716

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