Memory device and system including the same
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United States of America Patent
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Issued Date -
Mar 1, 2018
app pub date -
Nov 14, 2016
filing date -
Aug 23, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. The memory device may include a refresh controller configured to control a refresh operation of a bank according to a refresh control signal. The memory device may include a repair controller configured to control a repair operation of the bank according to a redundancy signal.
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