PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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app pub date -
Oct 14, 2016
filing date -
Aug 31, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A package structure includes a substrate, a patterned solder resist layer, a plurality of solders, a chip and a polymer gel. The substrate includes a plurality of solder pads. The patterned solder resist layer is disposed on the substrate and includes a plurality of stepped openings. The stepped openings expose the solder pads respectively. The solders are disposed on the solder pads and located in the stepped openings respectively. The chip is disposed on the substrate and includes an active surface and a plurality of bond pads. The bond pads are disposed on the active surface and connected to the solder pads by the solders. The polymer gel fills between a top surface of the patterned solder resist layer and the active surface. The polymer gel at least surrounds a disposing region of the solders and fills between two adjacent solders.
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