Method for fabricating memory device
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United States of America Patent
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Dec 18, 2018
Grant Date -
Mar 1, 2018
app pub date -
Nov 16, 2016
filing date -
Aug 30, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A method for fabricating a memory device is provided. In the method, a first gate dielectric layer is formed on a substrate in a first region. A second gate dielectric layer is formed on the substrate in a second region and a third region. A first conductive layer is formed on the substrate. A first dielectric layer is directly formed on the first conductive layer. One portion of the first dielectric layer, one portion of the first conductive layer, and one portion of the second gate dielectric layer in the second region are removed. A third gate dielectric layer and a second conductive layer are formed sequentially on the substrate in the second region. A third conductive layer and a second dielectric layer are formed sequentially on the substrate. Isolation structures are formed in the substrate. Here, the isolation structures penetrate the second dielectric layer and extend into the substrate.
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