Multiple input signature register analysis for digital circuitry
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United States of America Patent
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Jan 22, 2019
Grant Date -
Mar 8, 2018
app pub date -
Dec 30, 2016
filing date -
Sep 6, 2016
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Abstract
A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.
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Patent Owner(s)
- AGILENT TECHNOLOGIES TEXAS INSTRUMENTS INCORPORATED
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Maheshwari, Naman | Ghaziabad, IN | 3 | 13 |
Narayanan, Prakash | Bangalore, IN | 45 | 225 |
Pradeep, Wilson | Bangalore, IN | 20 | 50 |
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