Multi-register gather instruction
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United States of America Patent
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Jan 15, 2019
Grant Date -
Mar 15, 2018
app pub date -
Sep 19, 2017
filing date -
Dec 23, 2011
priority date (Note) -
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Abstract
A processor fetches a multi-register gather instruction that includes a destination operand that specifies a destination vector register, and a source operand that identifies content that indicates multiple vector registers, a first set of indexes of each of the vector registers that each identifies a source data element, and a second set of indexes of the destination vector register for each identified source element. The instruction is decoded and executed, causing, for each of the first set of indexes of each of the vector registers, the source data element that corresponds to that index of that vector register to be stored in a set of destination data elements that correspond to the second set of identified indexes of the destination vector register for that source data element.
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