Importance

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Abstract

A time de-interleaving circuit is located at a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a plurality of information units, which include a plurality of data units and a plurality of common units. The time de-interleaving circuit includes: a data unit access address generator, generating a plurality of data unit access addresses according to a first address sequence to accordingly access the plurality of data units in a memory; and a common unit access address generator, generating a plurality of common unit access addresses according to a second address sequence to accordingly access the plurality of common units in the memory. The second address sequence is a reverse sequence of the first address sequence.

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First Claim