Interconnect arrangement with stress-reducing structure and method of fabricating the same
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United States of America Patent
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Feb 12, 2019
Grant Date -
Mar 15, 2018
app pub date -
Nov 9, 2017
filing date -
Jan 23, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.
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