Backside spacer structures for improved thermal performance

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United States of America Patent

PATENT NO 10153224
APP PUB NO 20180076110A1
SERIAL NO

15264957

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Abstract

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Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Agarwal, Rahul Waterford, US 158 956
England, Luke Saratoga Springs, US 35 471
Zhang, Haojun Schenectady, US 13 140

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