Automatic detection of change in PLL locking trend
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United States of America Patent
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Oct 2, 2018
Grant Date -
Apr 19, 2018
app pub date -
Dec 18, 2017
filing date -
Apr 21, 2016
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.
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