Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor

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United States of America Patent

PATENT NO 10202583
APP PUB NO 20180195049A1
SERIAL NO

15818934

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Abstract

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A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.

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Patent Owner(s)

  • MICRON TECHNOLOGY INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ramaswamy, Durai Vishak Nirmal Boise, US 235 1263

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