TEST MODE CONTROL CIRCUIT
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United States of America Patent
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Issued Date -
Sep 13, 2018
app pub date -
May 10, 2018
filing date -
May 10, 2018
priority date (Note) -
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Abstract
A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.
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