Semiconductor memory device
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United States of America Patent
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Sep 17, 2019
Grant Date -
Sep 13, 2018
app pub date -
May 11, 2018
filing date -
Mar 2, 2016
priority date (Note) -
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Abstract
A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
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