Phase adjusting circuit, inverter circuit, and power supply system
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United States of America Patent
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Oct 15, 2019
Grant Date -
Oct 4, 2018
app pub date -
Feb 6, 2018
filing date -
Mar 31, 2017
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A phase adjusting circuit is provided that can highly precisely adjust frequencies throughout the entire frequency range to be dealt with. A PLL circuit includes: a reference-signal input terminal from which a reference signal is input; a feedback-signal input terminal from which a feedback signal is input; and an output terminal from which an output signal based on a phase difference between the reference signal and the feedback signal is output. A filter circuit is connected to the reference-signal input terminal and the output terminal, and causes a phase of the reference signal to be delayed when the oscillation frequency of an inverter circuit including the PLL circuit falls in a high range. A delay circuit is connected to the output terminal, and causes the output signal to be delayed when the oscillation frequency of the inverter circuit falls in a low range lower than the high range.
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