PHASE CALIBRATION METHOD AND ASSOCIATED PHASE LOCKED LOOP CIRCUIT

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United States of America Patent

APP PUB NO 20180294947A1
SERIAL NO

15690834

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A phase calibration method for a phase locked loop (PLL) circuit in a wireless communication device includes: calculating a header phase error of a header sub-frame of a frame in an input signal and a pilot phase error of a pilot sub-frame of the frame, wherein the header sub-frame and the pilot sub-frame are known data; generating an estimated phase error according to a relationship between the header phase error and the pilot phase error; generating a phase compensating signal according to the estimated phase error and a filtered signal; adjusting the input signal according to the phase compensating signal to generate a compensated input signal; detecting a phase error between a data sub-frame corresponding to the pilot sub-frame in the compensated input signal and a reference signal; and generating the filtered signal according to the phase error.

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Patent Owner(s)

Patent OwnerAddress
MSTAR SEMICONDUCTOR INC4F-1 NO 26 TAI-YUAN ST CHU PEI HSINCHU HSIEN 302

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHENG, Kai-Wen Hsinchu Hsein, TW 94 399
CHO, Ting-Nan Hsinchu Hsien, TW 10 1
TUNG, Tai-Lai Hsinchu Hsien, TW 112 174

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