SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREFOR

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United States of America Patent

APP PUB NO 20190122703A1
SERIAL NO

16229776

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Abstract

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A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATIONTOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ishii, Yuichiro Tokyo, JP 59 364
Saito, Yoshikazu Tokyo, JP 82 730
Tanaka, Shinji Tokyo, JP 329 3474
Tsukude, Masaki Tokyo, JP 121 3067

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