Ferroelectric memory plate power reduction
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United States of America Patent
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Apr 14, 2020
Grant Date -
Nov 14, 2019
app pub date -
May 9, 2018
filing date -
May 9, 2018
priority date (Note) -
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Abstract
Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.
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