Static random access memories with programmable impedance elements and methods and devices including the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 15, 2020
Grant Date -
Nov 14, 2019
app pub date -
Nov 12, 2018
filing date -
May 13, 2016
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully