TIME-TO-DIGITAL CONVERTER, DIGITAL PHASE-LOCKED LOOP, METH-OD FOR OPERATING A TIME-TO-DIGITAL CONVERTER, AND METHOD FOR A DIGITAL PHASE-LOCKED LOOP
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United States of America
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Mar 2, 2017
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Mar 2, 2017
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Abstract
A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
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