RECEIVER EQUALIZATION AND STRESSED EYE TESTING SYSTEM

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20200025824A1
SERIAL NO

16039945

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.

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Patent Owner(s)

Patent OwnerAddress
FUTUREWEI TECHNOLOGIES INC1700 ALMA DRIVE SUITE 500 PLANO TX 75075

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Li, Yongyao Chengdu, CN 22 25
Liu, Xusheng Shenzhen, CN 8 10
Zhao, Gang Chandler, US 145 1549

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