HYBRID ITERATIVE ERROR CORRECTING AND REDUNDANCY DECODING OPERATIONS FOR MEMORY SUB-SYSTEMS
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United States of America
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Issued Date -
Jan 23, 2020
app pub date -
Jul 23, 2018
filing date -
Jul 23, 2018
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Abstract
Data stored on each of a set of memory components can be read. Corresponding data stored on a number of the set of memory components that cannot be decoded using an error correction code decoding operation can be identified. A determination can be made whether the number of the set of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. Responsive to determining that the number of the set of memory components that include the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device, can perform a redundancy error correction decoding operation to correct the data stored on each of the set of memory components.
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