GATE SPACER FORMATION FOR SCALED CMOS DEVICES

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20200027795A1
SERIAL NO

16037915

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Disclosed are methods of forming a CMOS device. One non-limiting method may include providing a gate structure atop a substrate, and forming a first spacer over the gate structure. The method may include removing the first spacer from just an upper portion of the gate structure by performing an angled reactive ion etch or angled implantation disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may further include forming a second spacer over the upper portion of the gate structure and the first spacer along a lower portion of the gate structure. A thickness of the first spacer and the second spacer along the lower portion of the gate structure may be greater than a thickness of the second spacer along the upper portion of the gate structure.

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Patent Owner(s)

  • VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sung, Min Gyu Essex, US 129 421
Varghese, Sony Manchester, US 25 23

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