GRAPHIC PROCESSOR UNIT TOPOLOGY-AWARE ALL-REDUCE OPERATION

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20200051201A1
SERIAL NO

16058087

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Abstract

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A computer-implemented topology-aware all-reduce method for an environment including a plurality of systems is provided. Each system of the systems includes a plurality of computing modules. The computer-implemented topology-aware all-reduce method according to aspects of the invention includes locally partitioning and scattering data slices among the computing modules of each system to produce local summation results. The local summation results are copied from the computing modules to corresponding host memories of the f systems. A cross system all-reduce operation is executed among the systems to cause an exchange of the local summation results across the host memories and a determination of final summation partitions from the local summation results. The final summation partitions are copied from the host memories to the corresponding computing modules of each system. The final summation partitions are forwarded to all graphical processing units (GPUs) to cause a determination of final summation results therefrom.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATIONNEW ORCHARD ROAD ARMONK NY 10504

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
REN, YUFEI East Setauket, US 25 223
Wu, Xingbo Chicago, US 3 16
Zhang, Li Yorktown Heights, US 2407 31906
Zhang, Wei Elmsford, US 2311 17769

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