VERTICAL FIELD EFFECT TRANSISTORS WITH SELF ALIGNED SOURCE/DRAIN JUNCTIONS
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United States of America
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Issued Date -
Feb 13, 2020
app pub date -
Oct 15, 2019
filing date -
Oct 15, 2019
priority date (Note) -
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Abstract
A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.
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