Bypass structure

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United States of America Patent

PATENT NO 10640366
APP PUB NO 20200102212A1
SERIAL NO

16161404

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Abstract

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An integrated CMOS-MEMS device includes a first substrate having a CMOS device, a second substrate having a MEMS device, an insulator layer disposed between the first substrate and the second substrate, a dischargeable ground-contact, an electrical bypass structure, and a contrast stress layer. The first substrate includes a conductor that is conductively connecting to the CMOS devices. The electrical bypass structure has a conducting layer conductively connecting this conductor of the first substrate with the dischargeable ground-contact through a process-configurable electrical connection. The contrast stress layer is disposed between the insulator layer and the conducting layer of the electrical bypass structure.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Kuei-Sung Kaohsiung, TW 90 575
Hsieh, Eason Hsinchu, TW 3 0
Lai, Fei-Lung New Taipei, TW 42 509

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