EMBEDDED SAR-ADC WITH LEAST SIGNIFICANT BIT SKIPPING BASED RELU ACTIVATION FUNCTION
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United States of America Patent
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Issued Date -
Apr 4, 2024
app pub date -
Dec 14, 2023
filing date -
Sep 5, 2023
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Abstract
Systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (MAC) operations during a computation phase, and a successive approximation register (SAR) coupled to the capacitor ladder, the SAR to control the capacitor ladder to digitize results of the multi-bit MAC operations during a digitization phase.
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