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Abstract

The present disclosure provides a content addressable memory (CAM). The CAM includes a CAM register configured to store a mapping table, N comparators coupling to the CAM register, and N multiplexers coupling to the N comparators respectively and to the CAM register. The mapping table includes first addresses and second addresses. Each one of the first addresses corresponds to one of the second addresses. Each of the N comparators is configured to compare the first addresses with one of N input signals, where N is an integer greater than 1. The N input signals come from N microcontroller units. The N multiplexers is configured to generate N output signals. At least one of the N output signals is obtained according to the mapping table and a comparison output by one comparator of the N comparators.

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First Claim