Importance

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Abstract

In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and M redundant banks, where each of P, N and M is a positive integer, and N is greater than M The I/O circuit is coupled to the P groups of banks and configured to direct P×N pieces of data to or from P×N working banks, respectively. One of the M redundant banks is coupled with at least two main banks of the N main banks through the I/O circuit. The I/O control logic is configured to in responding to K main banks of the P groups of banks failed, determine the P×N working banks including K redundant banks of P×M redundant banks, where K is a positive integer not greater than P, and control the I/O circuit to direct P×N pieces of data to or from the P×N working banks, respectively.

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First Claim