TESTING ADCs
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United States of America Patent
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Issued Date -
Jun 6, 2024
app pub date -
Mar 31, 2022
filing date -
Mar 31, 2021
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit portion is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, and an input for a reference signal. The SAR ADC is arranged to generate a feedback signal having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation of the comparison of the reference duty cycle and the feedback duty cycle.
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