MEMORY MODULE PROVIDING DISTINCT SIGNALING INTERFACES VIA AN OPEN-DRAIN OUTPUT FOR DISTINCT OPERATIONS

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United States of America Patent

APP PUB NO 20240232105A1
SERIAL NO

18413017

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Abstract

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A memory subsystem is operable with a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. The memory subsystem controller has an open drain output, and is configured to provide a first signaling interface via the open drain output during normal operations and a second signaling interface via the open drain output during an initialization operation. The second signaling interface is distinct from the first signaling interface and the initialization operation is distinct from any of the normal operations. The first signaling interface is used by the memory subsystem controller to indicate a parity error in response to a parity error having occurred during the normal operations. The second signaling interface is used by the memory subsystem controller to output a signal related to initialization operation sequences during the initialization operation.

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Patent Owner(s)

Patent OwnerAddress
NETLIST INCIRVINE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Hyun Ladera Ranch, US 325 5301

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